1. Field of the Invention
The present invention relates to an evaluation device for a bit error. In particular, the present invention relates to a pull-in circuit for a pseudo-random pattern (hereinafter, it may be described as "PN pattern", wherein "PN" is an abbreviation for "Pseudo Noise"), which carries out a pull-in operation of a PN pattern transmitted from a transmitter device to a receiver device and a reference PN pattern generated by a PN pattern generation circuit in a receiver device.
2. Description of Related Art
In order to evaluate a bit error of a receiving signal of a communication device, a transmission device, a transmission line or the like, a PN pattern is used frequently. In an evaluation device for evaluating a bit error of the receiving signal, the receiving signal is compared with a reference signal generated in a receiver device, so that a bit error is detected.
In the concrete, when a PN pattern generated in a transmitter device is received by a receiver device through a device, transmission device or the like, the received PN pattern is compared with a reference PN pattern generated by a PN pattern generation circuit in a receiver so that a bit error is detected. In such an evaluation device for a bit error, a pull-in circuit for a PN pattern is required in order to synchronize the received PN pattern with the reference PN pattern.
FIG. 4 shows a block diagram of a conventional pull-in circuit for a PN pattern. As shown in FIG. 4, reference numeral 1 denotes a receiving-data input terminal, 3 denotes a bit error detection output terminal, 4 denotes a parallel PN pattern generation circuit, 8 denotes a delay circuit, 9 denotes a bit error detection circuit, 10 denotes a latch data input terminal of the parallel PN pattern generation circuit 4, 11 denotes a latch signal input terminal of the parallel PN pattern generation circuit 4 and 12 denotes a latch signal input terminal.
In the above-mentioned elements, the parallel PN pattern generation circuit 4 which outputs a parallel PN pattern having n bits, will be explained.
FIG. 7 shows a block diagram of a series PN pattern generation circuit which is a prototype circuit of the parallel PN pattern generation circuit 4. The series PN pattern generation circuit outputs a serial PN pattern. The series PN pattern generation circuit comprises a shift register having x flip-flop circuits 21-1 to 21-x, and an exclusive OR circuit 23 which operates an exclusive OR of the outputs from the first flip-flop circuit 21-1 and the jth flip-flop circuit 21-j and which outputs the result of the exclusive OR operation to the Xth flip-flop circuit 21-X. In FIG. 7, reference numeral 21 denotes a serial PN pattern input terminal, and therefrom a PN pattern having x stages outputs in (2.sup.x -1) bits cycle. The characteristic of the series PN pattern generation circuit is expressed the following characteristic equation, if the number of j is a proper value determined by each stage number. EQU f(a)=a.sup.x +a.sup.j +1 (1)
From the characteristic equation, a reference PN pattern is determined.
In a measuring instrument operating at higher speed, a serial signal is converted to a parallel signal, so that a signal processing is carried out at lower speed. That is, on a transmitter side, a parallel signal is generated and is converted into a serial signal to be processed at higher speed at a multiplexing circuit after a signal processing of the parallel signal. On a receiver side, the serial signal is received and is converted into a parallel signal to be processed at lower speed at a dividing circuit. Subsequently, a signal processing of the parallel signal is carried out.
The PN pattern generation circuit outputting a parallel PN pattern is called a parallel PN pattern generation circuit. In such a parallel PN pattern generation circuit, a parallel PN pattern is obtained by converting a serial PN pattern into a parallel PN pattern. Because a pattern obtained after the sampling in a constant cycle is the same PN pattern as before the sampling, each bit outputted from a parallel PN pattern generation circuit forms the same PN pattern.
FIG. 8 shows a block diagram of a concrete configuration of a parallel PN pattern generation circuit 4 which outputs a parallel PN pattern. The parallel PN pattern generation circuit 4 has flip-flop circuits 34-1 to 34-n for inputting n parallel signals and an exclusive OR circuit 36 for operating the following PN pattern. Further, the parallel PN pattern generation circuit 4 has a latch data input terminal 31, a latch signal input terminal 32 and selection circuits 35-1 to 35-n to input initial values to the flip-flops 34-1 to 34-n. When a PN pattern is outputted from the parallel PN pattern generation circuit 4, the selection circuits 35-1 to 35-n select the output from the exclusive OR circuit 36. On the other hand, when initial values are set to the flip-flop circuits 34-1 to 34-n, the selection circuits 35-1 to 35-n select the input of the latch data input terminal 31 according to the status of the latch signal input terminal 32.
The operation of a pull-in circuit for a PN pattern shown in FIG. 4 will be explained with reference to a time chart as shown in FIG. 5. In FIG. 5, in order to explain the operation, each bit of a receiving data is named PN(1), PN(2) or the like. In this case, it is assumed that a bit error occurs at the bit PN(2n+2) so that the pattern is received erroneously.
A serial receiving data to be measured for a bit error, which is received by a receiver device from the receiving-data input terminal 1, is converted into a parallel receiving data having n bits, and thereafter the parallel receiving data is inputted to the pull-in circuit. On the other hand, a latch signal is inputted to a latch signal input terminal 12 so that the receiving data is inputted to the flip-flop circuits in a parallel PN pattern generation circuit 4. As a result, the receiving data is synchronized with the PN pattern outputted from the parallel PN pattern generation circuit 4, so that a bit error measurement can be carried out.
A receiving data is inputted to flip-flop circuits, so that the parallel PN pattern generation circuit 4 generates a reference parallel PN pattern having n bits for a bit error measurement by using the bits PN(1) to PN(n) inputted thereto as initial values.
The receiving data is compared with the reference PN pattern by delaying the receiving data at a delay circuit 8 while the receiving data and the reference PN pattern are carried out the pull-inoperation. The bits outputted from the delay circuit 8 are compared with those outputted from the parallel PN pattern generation circuit 4 corresponding thereto at the bit error detection circuit 9. In the concrete, as shown in the time chart of FIG. 5, the delay circuit 8 outputs a receiving data to delay the output for one clock, so that the bits outputted from the delay circuit 8 are compared with those outputted from the parallel PN pattern generation circuit 4 corresponding thereto at the bit error detection circuit 9. As a result, the bit error detection circuit 9 outputs the result of the comparison to the bit error detection output terminal 3. In this case, because the bit PN(2n+2) is received erroneously, a bit error detection signal is generated toward the bit PN(2n+2), and is outputted to the bit error detection output terminal 3.
As described above, in a conventional pull-in circuit for PN pattern, a receiving data inputted into the receiving-data input terminal 1 is inputted to the parallel PN pattern generation 4 by a latch signal inputted to the latch signal input terminal 12. The parallel PN pattern generation 4 outputs the reference PN pattern generated by using the inputted values as initial values and synchronized with a receiving data, so that the pull-in operation is carried out. During the pull-in operation, a latch signal is inputted to the latch signal input terminal 12 at an arbitrary timing. Therefore, there is possibility that the parallel PN pattern generation circuit 4 inputs the bit having a bit error, so that the parallel PN pattern generation 4 generates a reference PN pattern by using erroneous initial values.
The example of the above-mentioned case is shown in a time chart of FIG. 6. FIG. 6 shows the time chart to explain the operation of a conventional pull-in circuit as shown in FIG. 4 when the bit error measurement cannot be carried out. In the time chart of FIG. 6, each bit of the signal inputted into the receiving-data input terminal 1 is named PN(1), PN(2) or the like. Further, it is assumed that a bit error occurs at the bit PN(n+2).
After the reception of the receiving data, a latch signal is inputted to the latch signal input terminal 12 in order to carry out the pull-in operation. Because of the latch signal, initial values are set to the parallel PN pattern generation circuit 4. However, a bit error occurs at the receiving data latched by inputting the latch signal, so that the erroneous data is set to the parallel PN pattern generation circuit 4. Therefore, the following state of the parallel PN pattern generation circuit 4 outputs another unknown pattern which is not synchronized with the receiving data. As a result, because the receiving data is not synchronized with the reference data, a bit error measurement cannot be carried out. Subsequently, it is detected that the receiving data is not synchronized with the reference data. It is necessary that the latch signal is inputted again to latch the receiving data having no bit errors.
That is, in a conventional pull-in circuit for PN pattern, the receiving data inputted into the receiving-data input terminal 1 is inputted to the parallel PN pattern generation circuit 4 by the signal inputted to the latch signal input terminal 12 at an arbitrary timing, so that the pull-in operation of the receiving data and the reference data is carried out. There is possibility to input the bit having a bit error to the parallel PN pattern generation circuit 4. In this case, it is detected that the receiving data is not synchronized with the reference data, so that it is necessary to carry out the pull-in operation again. As a result, there is a problem that it takes longer to carry out the pull-in operation.